document # sram116 rev c revised march 2010 p4c164ll very low power 8kx8 static cmos ram features v cc current (commercial/industrial) operating: 55 ma cmos standby: 3 a access times 80/100 (commercial or industrial) 90/120 (military) single 5 volts 10% power supply easy memory expansion using ce 1 , ce 2 and oe inputs common data i/o three-state outputs fully ttl compatible inputs and outputs advanced cmos technology automatic power down packages 28-pin 300 and 600 mil dip 28-pin 330 mil sop functional block diagram pin config urations dip (p5, p6, c5-1), sop (s5) top view description the p4c164ll is a 64k density low power cmos static ram organized as 8kx8. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5v10% tolerance power supply. access times of 80 and 100 ns are available for commercial and industrial temperatures; access times of 90 and 100 ns are available for military temperature. cmos is utilized to reduce power consumption to a low level. the p4c164ll device provides asynchronous operation with matching access and cycle times. memory locations are specifed on address pins a 0 to a 12 . reading is accomplished by device selection ( ce 1 low, ce 2 high ) and output enabling ( oe ) while write enable ( we ) remains high. by presenting the address under these conditions, the data in the addressed memory loca - tion is presented on the data input/output pins. the input/ output pins stay in the high z state when either ce 1 or oe is high or we or ce 2 is low. package options for the p4c164ll include 28-pin 300 and 600 mil dip and 28-pin 330 mil sop packages.
p4c164ll - very low power 8k x 8 static cmos ram page 2 document # sram116 rev c dc electrical characteristics (over recommended operating temperature & supply voltage) (2) symbol parameter min max unit v cc supply voltage with respect to gnd -0.5 7.0 v v term terminal voltage with respect to gnd (up to 7.0v) -0.5 vcc + 0.5 v t a operating ambient temperature -55 125 c s tg storage temperature -65 150 c i out output current into low outputs 25 ma i lat latch-up current > 200 ma maximum r atings (1) recommen ded operating temperature & supply voltage grade ambient temp supply voltage commercial 0c to 70c 4.5v v cc 5.5v industrial -40c to +85c 4.5v v cc 5.5v military -55c to +125c 4.5v v cc 5.5v sym parameter test conditions min max unit v oh output high voltage (i/o 0 - i/o 7 ) i oh = -1ma, v cc = 4.5v 2.4 v v ol output low voltage (i/o 0 - i/o 7 ) i ol = 2.1ma 0.4 v v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage -0.5 (3) 0.8 v i li input leakage current gnd v in v cc com / ind -2 +2 a military -5 +5 i lo output leakage current gnd v out v cc ce 1 v ih com / ind -2 +2 a military -10 +10 i sb v cc current ttl standby current (ttl input levels) v cc = 5.5v, i out = 0 ma ce 1 = v ih or ce 2 = v il com / ind 100 a military 400 i sb1 v cc current cmos standby current (cmos input levels) v cc = 5.5v, i out = 0 ma ce 1 v cc - 0.2v or ce 2 0.2v com / ind 3 a military 25 notes: 1. stresses greater than those listed under maximum r atings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air fow. 3. transient inputs with v il and i il not more negative than C3.0v and C100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested.
p4c164ll - very low power 8k x 8 static cmos ram page 3 document # sram116 rev c capacita nces (4) symbol parameter test conditions max unit c in input capacitance v in = 0v 7 pf c out output capacitance v out = 0v 9 pf power dissipatio n characteristics vs. speed symbol parameter temperature range * -80 -90 -100 -120 unit i cc dynamic operating current com / ind / military 55 55 55 55 ma * tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. the device is continuously enabled for writing, i.e. ce 1 and we v il (max), oe is high. switching inputs are 0v and 3v. sym parameter -80 -90 -100 -120 unit min max min max min max min max t rc read cycle time 80 90 100 120 ns t aa address access time 80 90 100 120 ns t ac chip enable access time 80 90 100 120 ns t oh output hold from address change 10 10 10 10 ns t lz chip enable to output in low z 10 10 10 10 ns t hz chip disable to output in high z 30 30 30 30 ns t oe output enable low to data valid 40 40 40 40 ns t olz output enable low to low z 5 5 5 5 ns t ohz output enable high to high z 20 20 20 20 ns t pu chip enable to power up time 0 0 0 0 ns t pd chip disable to power down time 80 90 100 120 ns ac electrical characteristicsread cycle (over recommended operating temperature & supply voltage)
p4c164ll - very low power 8k x 8 static cmos ram page 4 document # sram116 rev c timing waveform of read cycle no. 1 ( oe controlled) (1) timing waveform of read cycle no. 2 (address controlled) notes: 5. we is high for read cycle. 6. ce 1 is low, ce 2 is high and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce 1 transition low and ce 2 transition high. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specifed in figure 1. this parameter is sampled and not 100% tested. 9. read cycle time is measured from the last valid address to the frst transitioning address. 10. transitions caused by a chip enable control have similar delays ir - respective of whether ce 1 or ce 2 causes them. timing waveform of read cycle no. 3 ( ce 1 , ce 2 controlled)
p4c164ll - very low power 8k x 8 static cmos ram page 5 document # sram116 rev c ac characteristicswrite cycle (over recommended operating temperature & supply voltage) symbol parameter -80 -90 -100 -120 unit min max min max min max min max t wc write cycle time 80 90 100 120 ns t cw chip enable time to end of write 70 80 80 100 ns t aw address valid to end of write 70 80 80 100 ns t as address setup time 0 0 0 0 ns t wp write pulse width 60 60 60 60 ns t ah address hold time 0 0 0 0 ns t dw data valid to end of write 40 40 40 40 ns t dh data hold time 0 0 0 0 ns t wz write enable to output in high z 30 30 30 30 ns t ow output active from end of write 10 10 10 10 ns timing waveform of write cycle no. 1 ( we controlled) (6) notes: 11. ce 1 and we must be low, and ce 2 high for write cycle. 12. oe is low for this write cycle to show t wz and t ow . 13. if ce 1 goes high, or ce 2 goes low, simultaneously with we high, the output remains in a high impedance state 14. write cycle time is measured from the last valid address to the frst transitioning address.
p4c164ll - very low power 8k x 8 static cmos ram page 6 document # sram116 rev c ac test conditions truth table timing w aveform of write cycle no. 2 ( ce controlled) (6) input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 mode ce 1 ce 2 oe we i/o power standby h x x x high z standby standby x l x x high z standby d out disabled l h h h high z active read l h l h d out active write l h x l high z active figure 1. output load figure 2. thevenin equivalent * including scope and test fxture. note: because of the ultra-high speed of the p4c164ll, care must be taken when testing this device; an inadequate setup can cause a normal function - ing part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fngers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal refections, proper termination must be used; for example, a 50? test environment should be terminated into a 50? load with 1.77v (thevenin voltage) at the comparator input, and a 589? resistor must be used in series with d out to match 639? (thevenin resistance).
p4c164ll - very low power 8k x 8 static cmos ram page 7 document # sram116 rev c ordering in formation data rete ntion characteristics symbol parameter test condition min typ. * v cc = max v cc = unit 2.0v 3.0v 2.0v 3.0v v dr v cc for data retention 2.0 v i ccdr data retention current ce 1 v cc - 0.2v or ce 2 0.2v, v in v cc - 0.2v or v in 0.2v 1 2 3 4 a t cdr chip deselect to data retention time 0 ns t r ? operation recovery time t rc ns data rete ntion waveform * ta = +25c t rc = read cycle time ? this parameter is guaranteed but not tested.
p4c164ll - very low power 8k x 8 static cmos ram page 8 document # sram116 rev c plastic dual i n-lin e package (300 mil) pkg # p5 # pins 28 (300 mil) symbol min max a - 0.210 a1 - b 0.014 0.023 b2 0.045 0.070 c 0.008 0.014 d 1.345 1.400 e1 0.270 0.300 e 0.300 0.380 e 0.100 bsc eb - 0.430 l 0.115 0.150 0 15 plastic dual i n-lin e package (600 mil) pkg # p6 # pins 28 (600 mil) symbol min max a 0.090 0.200 a1 0.000 0.070 b 0.014 0.020 b2 0.015 0.065 c 0.008 0.012 d 1.380 1.480 e1 0.485 0.550 e 0.600 0.625 e 0.100 bsc eb 0.600 typ l 0.100 0.200 0 15
p4c164ll - very low power 8k x 8 static cmos ram page 9 document # sram116 rev c pkg # s5 # pins 28 (330 mil) symbol min max a 0.079 0.102 a1 0.000 0.008 b 0.012 0.020 c 0.004 0.008 d 0.701 0.717 e 0.050 bsc e 0.331 0.346 h 0.457 0.488 l 0.016 0.050 0 8 pkg # c5-1 # pins 28 (600 mil) symbol min max a - 0.232 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.490 e 0.500 0.610 ea 0.600 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0.005 - soic/sop small outli n e ic package ceramic dual i n-lin e package (600 mil)
p4c164ll - very low power 8k x 8 static cmos ram page 10 document # sram116 rev c revisions document number sram116 document title p4c164ll - very low power 8kx8 static cmos ram rev issue date origin ator description of change or oct-2005 jdb new data sheet a aug-2006 jdb added lead free designation b jun-2007 jdb corrected sop package details c mar-2010 jdb added military temperature range
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